Semiconductor Capital Equipment Technology


Rapid Thermal Processing (RTP)

I founded Micro C Technologies in 1996 in Grand Rapids, Michigan to develop a novel rapid thermal semiconductor capital equipment (US Patents: 5,951,896; 6,090,212; 6,007,635).  The RTXTM RTP processing tool was developed with scientific, engineering and economic basics to facilitate maximum flexibility in order to optimize any given RTP process.   This chamber was also developed to meet production and cost performance industry requirements.  It was designed with rigorous numerical analysis solutions of the governing fluid dynamics within the chamber.  After three of years of product development and field tests this patented, fully automated Class 1 compliant RTP system was successfully utilized for the following semiconductor processes:  salicidation of cobalt, the annealing activation of arsenic- doped silicon wafers, dry RTO and wet oxidation processes for metal gate transistors.  The Remote plasma nitridation process was also evaluated with this RTP chamber. I was invited to present this technology in a technical paper at the Centennial Anniversary of the American Chemical Society in 2002 in Philadelphia, PA (Wafer Processing in an RTXTM RTP Chamber with Device Side Emissivity Measurement and Temperature Control, (IBM invited paper), S. J. Lineberry and A. J. Davio, Electrochemical Society Proceedings, Volume 2002-11,  289).  

The design of this RTP wafer processing chamber began by addressing the surface reaction rate of a generic RTP process: 

Where T is device side surface reaction temperature, E is the activation energy, and PA  and PB  are the partial pressures and flow fluxes for reactants A and B respectively.  The reaction power laws are summarized by the exponents a and b.  R and k are rate equation constants.  In RTA processes such as arsenic or boron annealing  as well as titanium and cobalt salicidation, accurate determination of the wafer surface temperature, its uniformity and control are key to process optimization and repeatability.  Whereas in processes such as gate oxide formation and titanium nitridation, optimal process results are only achieved by careful optimization between the surface temperature and the local flow fluxes of oxygen and ammonia respectively.  The RTXTM chamber is designed specifically to enable precise measurement and control of the device side wafer temperature and facilitates accurate control of the local gas dynamics for RTP processes.


To determine the precise device side temperature, its surface emissivity must first be measured.  The average emissivity over all directions and wavelengths is given by:

Where εwf is the wafer front side emissivity, shown here as dependent on the wavelength, λ,  and integrated over the hemisphere of  0-2π and 0-π/2 for φ and θ respectively (1).  Eb denotes the reference Black Body energy.  Kirchhoff’s Law states the following equality under conditions of hemispherical collection of radiation (1):

Where ρ, ε and τ  are the wafer reflectivity, emissivity and transmission respectively.  However, it is reported that silicon has a transmission value of 1E-04, or near zero, at 25ºC (2) for wavelengths greater than 0.95 microns.  In such cases Kirchhoff’s Law can then be reduced to:

Where the wafer front side emissivity can be measured from a direct knowledge of its reflectivity.  

Figure 1 below shows the RTXTM RTP chamber.  The wafer is placed horizontally onto a platform and is heated from its backside by a multi-zone linear array of tungsten halogen lamps.  The platform is rotated by a magnetically coupled external drive mechanism.

Figure 1:  RTXTM RTP chamber with wafer front side emissivity instrument and back side multi-zone heater technology.  Also shown are the multiple gas injection and exhaust ports.

The emissivity instrument is located directly above the wafer as shown and it contains a single sapphire bent probe.  The emissivity instrument also contains a light source that emits a broad wavelength band with a peak of approximately 0.95 microns.  When a wafer is first introduced into the chamber, the emissivity probe is calibrated by turning it upwards towards the light source.   The signal of the sapphire probe is directed to a photo multiplier incorporating a band gap filter of less than or equal to 0.95 microns.  Once this incident energy , Ii, is measured, the probe is rotated downward towards the wafer surface to collect both the reflected energy, Ir, and the energy emitted from the wafer at the given temperature, Iw.  The emissivity light source is turned off while the probe is facing the wafer, and the Iw signal is then determined.  The following expression is used to calculate the wafer device side emissivity by substituting for the reflectivity in equation [4]:

The term γ  denotes the emissivity geometrical constant.  The use of a bent sapphire probe with a large numerical aperture orthogonal to both the emissivity light source and the wafer surface ensures the conformance to Kirchhoff’s Law requirement of hemispherical collection of both irradiation and reflected energy.  Furthermore, the use of a single probe eliminates any need for probe and cable calibrations.  The device geometry which represents surface roughness is integrated by rotating the wafer during measurement, and thus equation [5] yields an instantaneous value for the average device side emissivity.  This emissivity can be measured at any chosen step within the RTP process sequence.

Once the wafer emissivity is determined as described above, the multi-zone sapphire optical probes signals are corrected in accordance to Planck’s Law (3) and the wafer temperature in each measurement zone is determined within the limit of the accuracy of the photo multiplier instrumentation technology, which is calibrated in reference to a Black Body within ±1ºC in the range of 350°C to 1100°C (4).  An optional enhanced photo multiplier extends the operating temperature range down to 150°C to 800°C.  Each temperature measurement is then compared to a processing temperature set point and each back side heater zone is controlled via a multi-step PID algorithm. 

The RTXTM RTP chamber geometry incorporates multiple gas injection and exhaust ports that allow for the optimization of a variety of RTP processes.  This design feature of the RTP chamber is based on numerical solutions of the Navier-Stokes gas dynamics governing equations.  The equations using cylindrical coordinates for laminar flow in a rectangular cross-section between two parallel plates are (5):

Where ur and uz  are the velocities of reactant’s A and B, respectively, in the radial and vertical axes above the wafer.  P is the local dynamic pressure and ρ is the gas density.  


A numerical solution for the described gas flow within the RTXTM RTP chamber above is shown below in Figure 2 where the gas injection is from the right port of the chamber and the exhaust is to the left.

Figure 2:  Numerical solution to Navier-Stokes gas dynamics in RTXTM RTP chamber.  Laminar flow analysis showing laminar flow profiles and varying boundary layer immediately above the wafer with side gas injection and side exhaust


The velocity profile of the laminar flow over the wafer vicinity is clearly shown.  It is important to note how the laminar boundary layer varies as the flow traverses the wafer diameter.  Because the mass flux delivery to the wafer surface is inversely proportional to this boundary layer, the resultant RTP process uniformity will vary in accordance to the boundary layer non-uniformity.  

Figure 3 shows a flow profile in the RTXTM chamber where the flow is centrally injected and exhausted symmetrically from the right and left chamber ports.  

Figure 3:  Numerical solution to Navier-Stokes gas dynamics in RTXTM RTP chamber.  Laminar flow analysis showing laminar flow profiles and varying boundary layer immediately above the wafer with center gas injection and side exhausts.

It can be seen in Figure 3 that the velocity profiles immediately above the wafer surface are quite different than those shown in Figure 2.  Variations of the boundary layer immediately above the wafer surface affect mass transport and subsequently, the rate of reaction.  At higher pressure operations the boundary layers also play a significant role in determining the net temperature profile at each point over the surface of the wafer due to local values of convective heat transfer (6).  Such analysis of velocity profile guided the design of the RTXTM chamber and its multiple gas injection and exhaust ports as shown schematically in Figure 1.  Wafer rotation, which is achieved via a magnetically coupled external drive mechanism, is used to increase the thermal uniform distribution of the energy input into the back side of the wafer.  The gas injection and exhaust ports together with wafer rotation represent a very flexible chamber geometry for efficient optimization of a wide range of RTP process applications.  

Semiconductor Process Applications:

1. Cobalt Silicide Formation:

The in-situ emissivity measurement is key in measuring wafer processing temperature.  It can also be used in a novel way to determine the optimal processing temperature at which phase transformation reactions may take place.  The emissivity of a thin cobalt film on silicon was measured for temperatures up to 800°C.  This was performed at a pressure of 1 Torr with center injection and side exhausted nitrogen.  Figure 4 shows how the surface emissivity changes as the cobalt begins to react with the silicon substrate to form cobalt silicide.  The emissivity of the cobalt film changes suddenly from 0.350 at room temperature to 0.570 at 565°C and then remains relatively constant up to 800°C.  This indicates a phase transformation temperature for cobalt silicide which can be used in subsequent processing for process optimization.  Figure 4 also shows that there is no reaction with a cobalt film sputtered over a silicon wafer with a silicon oxide film.  The abrupt change of emissivity of this cobalt over SiO2 at approximately 740°C  is due to cobalt diffusion.    


1. Rapid Thermal Annealing:

 For standard RTA processes the chamber was configured with side gas injection and  exhaust.  The multi-zone temperature controller was optimized for the fastest ramp rate without any temperature overshoot of the desired annealing set point.  Typically, a 300 mm P-type silicon wafer was implanted with 3E15 As at 40 KeV.  This was annealed at 1000°C in nitrogen at 10 Torr for 10 seconds.  Figure 5 shows the wafer uniformity contour map of 49 data points with 3 mm edge exclusion.  The mean sheet resistance was 82.54 Ohms/square with a uniformity of  0.43% one standard deviation.

Figure 5:  Contour map of a 300 mm P-type As implant wafer (3E15 @ 40 KeV) after annealing for 10 seconds at 1000°C in 10 Torr of nitrogen.  Mean sheet resistance is 82.54 Ohms/square with a one sigma uniformity of 0.43%.

Steady state conduction heat transfer analysis by the authors indicates that a temperature difference of  up to 7°C could exist between the wafer back and device sides.  However when the annealing process time is reduced, as with shallower junctions, this temperature gradient would increase dramatically.  Experimental results of the As annealing process revealed that this difference was measured to be 19°C at 1000°C for 10 seconds.  Measuring and controlling device side temperature will become increasingly more important as shorter annealing processes are considered.

Four As implanted wafers each with different pattern densities were prepared.  These wafers were annealed at 900°C for 10 seconds in nitrogen.  Using the process temperature sensitivity, the effect of the pattern density on the actual local temperature was determined for three types of RTP systems as represented by the temperature difference between the patterned wafer and bare silicon implanted wafers.  Figure 6 shows that the RTXTM chamber, which employs back side heating, is practically pattern-independent. ΔT for the RTXTM is at 1.25°C maximum deviation for a 25% patterned density, while systems with dual-sided heating and top side heating resulted in maximum deviations of 4.2°C and 5.3°C respectively.

Figure 6:  Temperature deviation, ΔT (°C), due to increased device pattern density for three types of RTP heating systems.


2. RTP Oxidation:

 Rapid thermal oxidation of silicon is readily optimized in the RTXTM chamber.  At 760 Torr with center and side oxygen injection and side exhaust, the oxide growth rate temperature sensitivity is 1.09 Å/°C for a temperature range of 1050°C to 1100°C.  Within wafer uniformities of the oxide are well below 1% one sigma.  In a marathon oxidation run the total pooled data variance with 15 monitor wafers yielded a total temperature variation of 2.99°C for a 3 sigma standard deviation.  This clearly demonstrates that the RTXTM is a robust RTP tool for production- worthy semiconductor processing.

3. Metal Gate Selective Oxidation:

The trend is towards selective poly-metal gate oxidation (7).  In the RTXTM chamber, this selective oxidation is carried out by injecting water vapor from a Fujikin Corporation water vapor generator  (8,9).  The selective oxidation process relies on the optimization of the process temperature with minimum boron diffusion at the lowest water vapor concentration.  The lower water concentration minimizes the encroachment, or bird’s beaks, which enhances process yield.  Optimal throughput is achieved by this minimum thermal budget.  In the RTXTM chamber a high growth rate oxidation process matrix is shown in Figure 7 below.  High flow rates were used at 760 Torr to  minimize boundary layer thickness at the wafer surface.  Typical within wafer uniformity of the grown oxide is at 1.3 Å full range for a film thickness of 32 Å.

Figure 7:  Selective oxidation process matrix for metal gate process using Fujikin Corporation water vapor generator.

4. Remote Plasma Nitridation:

The nitridation of a gate oxide for improved dielectric constant and boron penetration barrier using remote plasma nitridation techniques (RPN) has been addressed extensively elsewhere (10-14).  The RTXTM chamber was equipped with a 13.56 MHz remote plasma chamber at the location of the Top Port shown in Figure 1.  Most of the RPN process development focused on increasing the nitrogen concentration at the top surface of the gate oxide at room temperature and at reduced pressures.  However, it was found that nitrogen profiles can be modified depending on the nitridation time and process temperature.  The results reported here were performed at 25°C and 50 mTorr pressure.  The RPN process was optimized by using a qualitative method of net added ellipsometric optical thickness of the gate oxide after nitridation.  Here, Table 1 shows results achieved using the RTXTM chamber with remote plasma nitridation of a gate oxide:

Table 1:  Remote plasma nitridation process parameters of a gate oxide

                                       at 50 mTorr and 25°C.

RF Power         Net Added                        Within Wafer

(Watts)         Optical Thickness (Å)           Range (Å)

200                    5.86                                     0.51

500                    8.20                                   1.20

Figure 8 below shows a nitrogen profile derived from SIMS analysis.  It can be seen that most of the added nitrogen is within the first 3Å of the gate oxide thickness.


Figure 8: SIMS analysis of  a Nitrogen profile in a remote plasma nitrided gate oxide at 50 mTorr and 500 Watts RF(13.56 MHz) power.

5. Ultra Shallow Junction Annealing:

Shallow junction annealing methods are emerging rapidly for low energy implants in order to overcome the 130 nm node barrier in Xj-Rs (15, 16).  The requirements for uniformly activating low energy implants are challenging because of the competition between the implant activation energy and its diffusion processes (17-20).  The goal is to activate the implant uniformly in as short a time period as possible and with minimum diffusion into the silicon.  To achieve this goal, an energy source to activate the implanted wafer in the RTXTM chamber was developed.  For maximum absorption efficiency by the silicon, this energy source was designed with the optimal short wavelength spectrum.  The energy distribution density across the wafer can be varied to achieve uniform implant activation.  The pulse duration can be controlled down to a few milliseconds.   A novel rapid wafer cooling technique was developed to quench the activated implant as rapidly as permitted by radiation and convective heat transfer.   Figure 9 below is an example of an actual heat up and cool down time profile of a thermocouple fitted silicon wafer.  It indicates a heat up rate of 283°C/second and a cool down rate of 276 °C/second.  Initial results show that using a boron dose of  1E15 cm-2 at 1KeV had an as implanted depth of 340 Å  at 1E18 atoms/cc as determined by SIMS analysis.  With an RTXTM-Ultra pulse as shown in Figure 9, a sheet resistance of 830 Ohms/square was measured by SRP.  The  junction depth at 1E18 atoms/cc was 420 Å.  This represents a technological advantage and capability in comparison to emerging techniques.  This work continues with a focus on optimizing pulse durations, wavelengths and within wafer uniformity.

Figure 9:  T-C Wafer Temperature-time profile after a short high energy pulse by  RTXTM new energy source for ultra shallow junction annealing.  Heat up rate is 283 °C/second and cool down rate to 700°C is 276 °C/second.